In recent years, as a memory to replace a flash memory that is approaching a limit of miniaturization, a resistance variable memory has been studied. As one example of the resistance change type storage element, a phase-change memory which uses chalcogenide (phase-change material) such as Ge2Sb2Te5 has been extensively studied.
A state of the phase-change material is changed to an amorphous state or a crystalline state by Joule heat generated by an applied current. A material in the amorphous state has a high resistance value, and a material in a crystalline state has a low resistance value. It is possible to exhibit a function as a storage element by correlating a change in the resistance value with information.
In an information rewriting operation for the phase-change memory, an applied current is controlled according to information to be written. In a reset operation, that is, an operation of writing a bit “0”, a large amount of current is caused to flow for a short period of time to dissolve the phase-change material, and then a current is suddenly reduced. Accordingly, the phase-change material is rapidly cooled down, and the phase-change material is changed to the amorphous state of high resistance. On the other hand, a set operation, that is, an operation of writing a bit “1”, allows a sufficient current to flow for a long period of time so as to hold the phase-change material in a crystalline state. The phase-change material is changed to the crystalline state of low resistance. In an operation of reading information, a constant potential difference is given to both ends of the storage element and a current flowing in the element is measured, and thereby a resistance value of the element is determined.
In the phase-change material, when a shape of the storage element becomes small, a current necessary for changing a state of the phase-change material is reduced. Therefore, in principle, miniaturization and multi-layerization are pursued to achieve high integration.
In PTLs 1 and 2 to be described below, as a method for high integration of the phase-change memory in addition to miniaturization, a technology related to multi-layerization is described. In PTL 1, a structure in which memory cells configured to have a recording layer made of a chalcogenide material and a cell selection diode are stacked through an insulation layer is described. In PTL 2, a technology of stacking a plurality of memory cells made of a cell selection transistor and a recording element in a height direction by forming a through hole in a stack body obtained by stacking a plurality of gate electrodes and gate insulation layers and forming a gate insulation film, a silicon layer to be a channel, and a chalcogenide layer to be a recoding layer on a side surface of the through hole is described. It is possible to increase area density of a memory cell and to achieve high integration by increasing the number of stacked memory cells in the height direction.